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october 2009 doc id 16518 rev 1 1/32 32 STP16DPP05 low voltage 16-bit constant current led sink driver with output error detection features low voltage power supply down to 3 v 16 constant current output channels adjustable output current through external resistor short and open output error detection serial data in/parallel data out 3.3 v mcu-driving capability output current: 3 to 40 ma 30 mhz clock frequency available in high thermal efficiency tssop exposed pad esd protection: 2 kv hbm, 200 v mm description the STP16DPP05 is a monolithic, low voltage, low current power 16-bit shift register designed for led panel displays. the device features a 16-bit serial-in, parallel-out shift register that feeds a 16-bit d-type storage register. in the output stage, sixteen regulated current sources are designed to provide 3 to 40 ma of constant current to drive the leds. the STP16DPP05 features open and short led detection on the outputs. the detection circuit checks for 3 different conditions that can occur on the output line: short to gnd, short to v o or open line. the data detection results are loaded in the shift registers and shifted out via the serial line output. the detection functionality is implemented without increasing the pin count, through a secondary function of the output enable and latch pin (dm1 and dm2 respectively). a dedicated logic sequence allows the device to enter or exit from detection mode. the STP16DPP05 output current can be adjusted through an external resistor to control the light intensity of the leds. led brightness is adjustable from 0% to 100% via the oe/dm2 pin. the STP16DPP05 guarantees a 20 v output driving capability, allowing users to connect more leds in series. the high 30 mhz clock frequency makes the device suitable for high data rate transmission. the 3.3 v supply is well suited for applications which interface a 3.3 v mcu. compared to a standard tssop package, the tssop with exposed pad increases heat dissipation capability by a factor of 2.5 so-24 tssop24 tssop24 (exposed pad) qsop-24 table 1. device summary order codes package packaging STP16DPP05mtr so-24 (tape and reel) 1000 parts per reel STP16DPP05ttr tssop24 (tape and reel) 2500 parts per reel STP16DPP05xttr tssop24 exposed pad (tape and reel) 2500 parts per reel STP16DPP05ptr qsop-24 2500 parts per reel www.st.com
contents STP16DPP05 2/32 doc id 16518 rev 1 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 error detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 phase one: entering error detection mode . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 phase two: error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 phase three: resuming normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.4 error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STP16DPP05 summary description doc id 16518 rev 1 3/32 1 summary description 1.1 pin connection and description figure 1. pin connection note: the exposed pad should be electrically conn ected to a metal land electrically isolated or connected to ground. table 2. typical current accuracy output voltage current accuracy output current v dd temperature between bits between ics 1.3 v 1% 2% 5 to 40 ma 3.3 v to 5 v 25 c
summary description STP16DPP05 4/32 doc id 16518 rev 1 table 3. pin description pin n symbol name and function 1 gnd ground terminal 2 sdi serial data input terminal 3 clk clock input terminal 4 le/dm1 latch input terminal - detect mode 1 (see operation principle) 5-20 out 0-15 output terminal 21 oe/dm2 input terminal of output enable (active low) - detect mode 1 (see operation principle) 22 sdo serial data out terminal 23 r-ext input terminal for an external resistor for constant current programming 24 v dd supply voltage terminal
STP16DPP05 electrical ratings doc id 16518 rev 1 5/32 2 electrical ratings 2.1 absolute maximum ratings stressing the device above the ratings listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other condition above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.2 thermal data table 4. absolute maximum ratings symbol parameter value unit v dd supply voltage 0 to 7 v v o output voltage -0.5 to 20 v i o output current 50 ma v i input voltage -0.4 to v dd v i gnd gnd terminal current 800 ma f clk clock frequency 50 mhz t j junction temperature range (1) 1. such absolute value is based on the thermal shutdown protection. -40 to +170 c table 5. thermal data symbol parameter value unit t a operating free-air temperature range -40 to +125 c t j-opr operating thermal junction temperature range -40 to +150 c t stg storage temperature range -55 to +150 c r thja thermal resistance junction- ambient (1) 1. according with jedec standard 51-7b so-24 42.7 c/w tssop24 55 c/w tssop24 (2) exposed pad 2. the exposed pad should be soldered directly to the pcb to obtain the thermal benefits. 37.5 c/w qsop-24 55 c/w
electrical ratings STP16DPP05 6/32 doc id 16518 rev 1 2.3 recommended operating conditions table 6. recommended operating conditions symbol parameter test conditions min. typ. max. unit v dd supply voltage 3.0 5.5 v v o output voltage 20 v i o output current outn 3 40 ma i oh output current serial-out +1 ma i ol output current serial-out -1 ma v ih input voltage 0.7 v dd v dd v v il input voltage -0.3 0.3 v dd v t wlat le/dm1 pulse width v dd = 3.0 v to 5.0 v 20 ns t wclk clk pulse width 10 ns t wen oe/dm2 pulse width 100 ns t setup(d) setup time for data 8 ns t hold(d) hold time for data 5 ns t setup(l) setup time for latch 8 ns f clk clock frequency cascade operation (1) 1. if the device is connected in cascade, it may not be possible ac hieve the maximum data transfer. please consider the timings carefully. 30 mhz
STP16DPP05 electrical characteristics doc id 16518 rev 1 7/32 3 electrical characteristics v dd = 3.3 v to 5 v, t a = 25 c, unless otherwise specified. table 7. electrical characteristics symbol parameter test conditions min. typ. max. unit v ih input voltage high level 0.7 v dd v dd v v il input voltage low level gnd 0.3 v dd v i oh output leakage current v oh = 20 v 1 a v ol output voltage (serial-out) i ol = 1 ma 0.4 v v oh output voltage (serial-out) i oh = -1 ma v dd -0.4v v i ol1 output current v o = 0.3 v, r ext = 4 k 4.75 5 5.25 ma i ol2 v o = 0.3 v, r ext = 1 k 19 20 21 i ol3 v o = 1.3 v, r ext = 497 38 40 42 i ol1 output current error between bit (all output on) v o = 0.3 v, i o = 5 ma r ext = 4 k 1 5 % i ol2 v o = 0.3 v, i o = 20 ma r ext = 980 0.5 3 i ol3 v o = 1.3 v, i o = 40 ma r ext = 490 0.5 3 r sin(up) pull-up resistor 150 300 600 k r sin(down) pull-down resistor 100 200 400 k i dd(off1) supply current (off) r ext = 1 k , i out = 20 ma, out 0 to 15 = off 5.4 7.5 ma i dd(off2) r ext = 497 , i out = 40 ma out 0 to 15 = off 8.0 9.5 i dd(on1) supply current (on) r ext = 1 k , i out = 20 ma, out 0 to 15 = on 5.5 7.5 i dd(on2) r ext = 497 , i out = 40 ma out 0 to 15 = on 8.1 9.5 thermal thermal protection 170 c
electrical characteristics STP16DPP05 8/32 doc id 16518 rev 1 v dd = 3.3 v to 5 v, t a = 25 c, unless otherwise specified. table 8. switching characteristics symbol parameter test conditions min typ max unit t plh1 propagation delay time, clk-outn , le/dm1 = h, oe/dm2 = l v ih = v dd v il = gnd c l = 10 pf i o = 20 ma v l = 3.0 v r ext = 1 k r l = 60 v dd = 3.3 v 35.5 44.5 ns v dd = 5 v 18.5 24 t plh2 propagation delay time, le/dm1-outn , oe/dm2 = l v dd = 3.3 v 41.5 50 ns v dd = 5 v 23 29 t plh3 propagation delay time, oe/dm2 -outn , le = h v dd = 3.3 v 45 54 ns v dd = 5 v 25 31 t plh propagation delay time, clk-sdo v dd = 3.3 v 15 21 31 ns v dd = 5 v 11 15 21 t phl1 propagation delay time, clk-outn , le/dm1 = h, oe/dm2 = l v dd = 3.3 v 13.7 18 ns v dd = 5 v 8.8 12.5 t phl2 propagation delay time, le/dm1-outn , oe/dm2 = l v dd = 3.3 v 17 22 ns v dd = 5 v 13 17 t phl3 propagation delay time, oe /dm2 -outn , le/dm1 = h v dd = 3.3 v 12.7 17 ns v dd = 5 v 9.5 13 t phl propagation delay time, clk-sdo v dd = 3.3 v 17.5 24 36 ns v dd = 5 v 12.5 17 25 t on output rise time 10~90% of voltage waveform v dd = 3.3 v 28 39 ns v dd = 5 v 17 23 t off output fall time 90~10% of voltage waveform v dd = 3.3 v 4.5 6 ns v dd = 5 v 3.5 5 t r clk rise time (1) 5000 ns t f clk fall time (1) 5000 ns 1. in order to achieve high cascade data transfe r, please consider tr /tf timings carefully.
STP16DPP05 equivalent circuit and outputs doc id 16518 rev 1 9/32 4 equivalent circuit and outputs figure 2. oe/dm2 terminal figure 3. le/dm1 terminal figure 4. clk, sdi terminal
equivalent circuit and outputs STP16DPP05 10/32 doc id 16518 rev 1 figure 5. sdo terminal figure 6. block diagram %. %. &
STP16DPP05 timing diagrams doc id 16518 rev 1 11/32 5 timing diagrams note: outn = on when dn = h outn = off when dn = l figure 7. timing diagram note: 1 latch and output enable terminals are level-sensitive and are not synchronized with rising or falling edge of clk signal. 2 when le/dm1 terminal is low level, the latch circuit holds previous set of data. 3 when le/dm1 terminal is high level, the latch circuit refreshes new set of data from sdi chain. 4 when oe/dm2 terminal is at low level, the output terminals out 0 to out 15 respond to data in the latch circuits, either ?1? for on or ?0? for off. 5 when oe/dm2 terminal is at high level, all output terminals are switched off. table 9. truth table clock le/dm1 oe/dm2 serial-in out0 ............. out7 ................ out15 sdo h l dn dn ..... dn - 7 ..... dn -15 dn - 15 l l dn + 1 no change dn - 14 h l dn + 2 dn + 2 ..... dn - 5 ..... dn -13 dn - 13 x l dn + 3 dn + 2 ..... dn - 5 ..... dn -13 dn - 13 x h dn + 3 off dn - 13
timing diagrams STP16DPP05 12/32 doc id 16518 rev 1 figure 8. clock, serial-in, serial-out table 10. enable io: shutdown truth table clock le/dm1 sdi 0 ........... sdi 7 ............ sdi 15 sh auto power-up outn h all = l active not active (1) 1. at power-up, the device starts in shutdown mode. off l no change no change no change no change h one or more = h not active active x (2) 2. undefined.
STP16DPP05 timing diagrams doc id 16518 rev 1 13/32 figure 9. clock, serial-in, latch, enable, outputs figure 10. outputs le/dm1 oe/dm2 outn outn
typical characteristics STP16DPP05 14/32 doc id 16518 rev 1 6 typical characteristics figure 11. output current vs. r-ext resistor table 11. output current vs. r-ext resistor r-ext ( ) output current (ma) 23700 1 11730 2 6930 3 4090 5 2025 10 1000 20 667 30 497 40 331 60 0 5000 10000 15000 20000 25000 0 10203040506070 current (ma) r external (ohm)
STP16DPP05 typical characteristics doc id 16518 rev 1 15/32 conditions: temperature = 25 c, v dd = 3.3 v; 5.0 v, i set = 3 ma; 5 ma; 10 ma; 20 ma; 50 ma; 60 ma. figure 12. i set vs. dropout voltage (v drop ) table 12. i set vs. dropout voltage (v drop ) iout (ma) avg (mv) @ 3.3 v avg (mv)@ 5.0 v 33637 57172 10 163 163 20 346 347 40 724 726 60 1080 1110 0 200 400 600 800 1000 1200 0 5 10 15 20 25 30 35 40 45 50 55 60 65 current (ma) min drop voltage (mv ) avg @ 3.3v avg @ 5.0v
typical characteristics STP16DPP05 16/32 doc id 16518 rev 1 t a = 25 c, vdd = 3.3 v; 5 v figure 13. output current vs. i ol (%) figure 14. idd on/off 0 1 2 3 4 5 6 7 8 9 10 11 12 0 5 10 15 20 25 30 35 40 45 50 55 60 65 iset (ma) idd (ma) avg idd on @ 5.0v avg idd on @ 3.3v avg idd off @ 5.0v avg idd off @ 3.3v
STP16DPP05 typical characteristics doc id 16518 rev 1 17/32 figure 15. power dissipation vs. package temperature note: the exposed pad should be soldered to the pcb to obtain the thermal benefits. figure 16. turn on output current characteristics (1) figure 17. turn off output current characteristics (2) electrical conditions: vdd = 3.3 v, vin = vdd, vled = 3.0 v, rl = 60 , cl = 10 pf ch1 (yellow) = oe/dm2 , ch2 (blue) = sdi, ch3 (purple) = vout, ch4 (green) = out 1. the reference level for the t on characteristics is 50% of oe/dm2 signal and 90% of output current 2. the reference level for the t off characteristics is 50% of oe/dm2 signal and 10% of output current
error detection mode functionality STP16DPP05 18/32 doc id 16518 rev 1 7 error detection mode functionality 7.1 phase one: entering error detection mode from the ?normal mode? condition the device can switch to ?error mode? by a logic sequence on the oe/dm2 and le/dm1 pins, as shown in the following table and diagram: after these five clk cycles, the device goes into ?error detection mode? and at the rising edge of the 6th clk cycle, the sdi data are ready for sampling. table 13. entering error detection mode - truth table clk12345 oe/dm2 hlhhh le/dm1 lllhl figure 18. entering error detection mode - timing diagram clk oe/dm2 le/dm1
STP16DPP05 error detection mode functionality doc id 16518 rev 1 19/32 7.2 phase two: error detection the 16 data bits must be set to ?1? in order for all the outputs to be on during error detection. the data are latched by le/dm1, after which the outputs are ready for the detection process. when the microcontroller switches the oe/dm2 to low, the device drives the leds to analyze if an open or short condition has occurred. the status of the leds is detected in at le ast 1 microsecond, and after this period the microcontroller sets oe/dm2 to high state and the output data detection result is sent to the microcontroller via sdo. error detection mode and normal mode both use the same data format. as soon as all the detection data bits are available on the serial line, the device may return to normal mode of operation. to re-detect the status, the device must first return to normal mode and reenter error detection mode. figure 19. detection diagram
error detection mode functionality STP16DPP05 20/32 doc id 16518 rev 1 figure 20. timing example for open and/or short-circuit detection d.u.t. d.u.t. d.u.t. d.u.t. d.u.t.
STP16DPP05 error detection mode functionality doc id 16518 rev 1 21/32 7.3 phase three: resuming normal mode the sequence for reentering normal mode is shown in the following table: note: for proper device operation, the ?entering error detection? sequence must be followed by a ?resume mode? sequence, it is not possible to insert consecutive equal sequences. 7.4 error detection conditions note: where: i o = the output current programmed by the r-ext , i odec = the detected output current in detection mode figure 22. detection circuit figure 21. resuming normal mode - timing diagram clk12345 oe/dm2 hlhhh le/dm1 lllll table 14. detection conditions (v dd = 3.3 to 5 v, temperature range -40 to 125 c) configuration detect mode detection results sw-1 or sw-3b open line or output short to gnd detected ==> i odec 0.5 x i o no error detected ==> i odec 0.5 x i o sw-2 or sw-3a short on led or short to v-led detected ==> v o 2.6 v no error detected ==> v o 2.3 v 16 STP16DPP05
error detection mode functionality STP16DPP05 22/32 doc id 16518 rev 1 figure 23. error detection sequence ig no re on the rising edge of first clk pulse after the detection, the sdo provides the output status f eedback with the sequence out 15; out 14?out 0. in this case all the outputs are in f ault condition (open or short) this oe/dm2 pulse put the device in normal mode condition af ter edm test turn on the output with the oe/dm2 pin and wait 1 s to have the correct output status acquisition. during this time a minimum of three clk pulses are required (2 at the beginning and 1 at the end) to rewrite the shif t register. oe/dm2 and le/dm1 sequence signals to start the error detection sequence feeding 16 bit of clk signal af ter entering the edm, the sdi signal, set to 1, is loaded in the shif t register this le/dm1 pulse latch the data to the outputs
STP16DPP05 package mechanical data doc id 16518 rev 1 23/32 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 15. qsop-24 mechanical data dim. mm. inch min typ max min typ max a 1.54 1.62 1.73 0.061 0.064 0.068 a1 0.1 0.15 0.25 0.004 0.006 0.010 a2 1.47 0.058 b 0.31 0.2 0.012 0.008 c 0.254 0.17 0.010 0.007 d 8.56 8.66 8.76 0.337 0.341 0.345 e 5.8 6 6.2 0.228 0.236 0.244 e1 3.8 3.91 4.01 0.150 0.154 0.158 e 0.635 0.025 l 0.4 0.635 0.89 0.016 0.025 0.035 h 0.25 0.33 0.41 0.010 0.013 0.016 < 8 0
package mechanical data STP16DPP05 24/32 doc id 16518 rev 1 figure 24. qsop-24 package dimensions
STP16DPP05 package mechanical data doc id 16518 rev 1 25/32 figure 25. qsop-24 tape and reel dimensions table 16. qsop-24 tape and reel dim. mm. inches min typ max min typ max r1 12.8 13 13.5 5.039 5.118 5.315 r2 330 129.921 r3 100 39.37 eint 16.4 6.457 e1 1.5 2 2.5 0.591 0.787 0.984 0.3+/-0.05 1 0 . 3 + / - 0 . 1 2.1 +/-0.1 2.0+/-0.1 4.0+/-0.1 1.75+/-0.1 16 +/-0.3 7.5+/-0.1 1.6 +1/-0.1 8 +/-0.1 6 . 5 + / - 0 . 1 1.5+1/0 0.3+/-0.05 1 0 . 3 + / - 0 . 1 2.1 +/-0.1 2.0+/-0.1 4.0+/-0.1 1.75+/-0.1 16 +/-0.3 7.5+/-0.1 1.6 +1/-0.1 8 +/-0.1 6 . 5 + / - 0 . 1 1.5+1/0 7217 8 11_c
package mechanical data STP16DPP05 26/32 doc id 16518 rev 1 table 17. tssop24 mechanical data dim. mm. inches min typ max min typ max a 1.1 0.043 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 d 7.7 7.9 0.303 0.311 e 4.3 4.5 0.169 0.177 e 0.65 bsc 0.0256 bsc h 6.25 6.5 0.246 0.256 k 0 8 0 8 l 0.50 0.70 0.020 0.028 figure 26. tssop24 package dimensions
STP16DPP05 package mechanical data doc id 16518 rev 1 27/32 table 18. tssop24 exposed pad mechanical data dim. mm inches min typ max min typ max a 1.2 0.047 a1 0.15 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 7.7 7.8 7.9 0.303 0.307 0.311 d1 4.7 5.0 5.3 0.185 0.197 0.209 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.5 0.169 0.173 0.177 e2 2.9 3.2 3.5 0.114 0.126 0.138 e 0.65 0.0256 k 0 8 0 8 l 0.45 0.60 0.75 0.018 0.024 0.030 figure 27. tssop24 exposed pad dimensions
package mechanical data STP16DPP05 28/32 doc id 16518 rev 1 table 19. tape and reel tssop24 and tssop24 exposed pad dim. mm. inches min typ max min typ max a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 22.4 0.882 ao 6.8 7 0.268 0.276 bo 8.2 8.4 0.323 0.331 ko 1.7 1.9 0.067 0.075 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 figure 28. tssop24 and tssop24 exposed pad tape and reel dimensions
STP16DPP05 package mechanical data doc id 16518 rev 1 29/32 table 20. so-24 mechanical data dim. mm. inches min typ max min typ max a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45(typ.) d 15.20 15.60 0.598 0.614 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 13.97 0.550 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 s (max.) 8 figure 29. so-24 package dimensions
package mechanical data STP16DPP05 30/32 doc id 16518 rev 1 table 21. tape and reel so-24 dim. mm. inches min typ max min typ max a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 30.4 1.197 ao 10.8 11.0 0.425 0.433 bo 15.7 15.9 0.618 0.626 ko 2.9 3.1 0.114 0.122 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 figure 30. so-24 tape and reel dimensions
STP16DPP05 revision history doc id 16518 rev 1 31/32 9 revision history table 22. document revision history date revision changes 22-oct-2009 1 initial release.
STP16DPP05 32/32 doc id 16518 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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